A Research Associate position in analysis and verification of novel cache algorithms is available at the School of Computer Science within the University of St Andrews. The position is a fixed-term position for 18 months, starting January 2017 or as soon as possible thereafter. The project involves understanding and developing the theoretical basis for such algorithms, formalising them using formal techniques of theorem proving and/or model checking, and developing formal analysis and correctness proofs for such algorithms.

This is part of the EPSRC-funded “C3:Scalable & Verified Shared Memory via Consistency-Directed Cache Coherence” (EP/M027317/1) project, a collaborative project with architecture researchers at the University of Edinburgh and at Intel Corporation Ltd, investigating high-performance cache coherence protocols. Our goal is to propose and verify a family of protocols that are aware of high-level programming models, including in particular those with so-called relaxed memory consistency models.

The particular direction at St Andrews under the direction of Dr Sarkar is to develop verification methods that will scale to the research cache coherence protocols being co-developed within the project. This is a new application area for formal methods, with performance and correctness both equally important. Thus, a background in one or more of Formal Methods, Compilers and Static Analysis, and Verification Tools is expected. Software development and/or formal proof development experience is invaluable.

For an informal discussion about the post you are welcome to contact Dr Susmit Sarkar.

Applications are particularly welcomed from women and other groups that are under-represented in Research posts at the University.

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