Title: “Shared-Memory Concurrency in the Real World: Working with Relaxed Memory Consistency”

Abstract:

Shared-memory concurrency is now mainstream, from phones to servers. However, real-world implementations do not validate the basic assumption of Sequential Consistency traditionally made in work on concurrent programming and verification. Instead, we get subtle relaxed consistency models. Furthermore, the consistency models of different hardware architectures vary widely and have often been poorly defined, while programming language models (aiming to abstract from hardware details) are different again.

This talk is about what relaxed consistency models we actually get on current mainstream systems: the x86 multiprocessor architecture, the IBM Power and ARM lines of multiprocessors, and in the new concurrency model in ISO C/C++11. Part of the challenge here is that neither hardware microarchitects nor low-level programmers (for operating systems or compilers) know exactly what you get, or what you should get. I will discuss the models that are getting some agreement/acceptance, and how we can use those models.