- When: 5th November 2019 14:00 - 15:00
- Where: Cole 1.33b
- Series: School Seminar Series
- Format: Seminar
Two important aspects in hardware design are the safe routing of signals between modules, and ensuring that ports are correctly connected. Well-known hardware description languages such as SystemVerilog, provide nominal checking over these aspects. Thus, leaving correctness checks over module orchestration to be performed post-design-time using static analyses, testing, and during synthesis.
Using a mixture of dependent and quantitative typing, we can lift external correctness checks over module connections directly into the type-system. With this approach we can detect more errors at design time, enhance the safety of our hardware designs, and thus increase design productivity.
In this talk I will introduce and discuss LightClick, an orchestration language for hardware design that exemplifies our approach. LightClick uses quantitative typing to ensure linear usage of ports, and dependent types to ensure that port compatibility is a decidable compile-time check. I will show how LightClick can be used to model simple hardware designs, how SystemVerilog stubs are generated from designs using staged interpretation.
Speaker Bio: Jan is a Research Associate at the University of Glasgow, who is interested in using state-of-the-art advances in programming language theory to build more trustworthy systems. Jan is currently involved in the Border Patrol project – a collaboration between the Universities of Heriot-Watt, Glasgow, and Imperial College London to explore how Dependent Typing and Session Typing can help make hardware design safer and secure.