Abstract:

This talk will demonstrate how model checking based verification of compilers and runtime systems can increase the confidence of parallel execution of programming languages, using two case studies.

As HPC systems continue to increase in scale, their mean time between failure decreases meaning reliability has become a major concern. I will present HdpH-RS, a parallel HPC language. HdpH-RS has a formal semantics, and a fault tolerant work stealing scheduler that has been verified with the SPIN model checker. At embedded scale, program transformations on stateful dynamic code can introduce bugs, race conditions and deadlock. I will present a parallel refactoring tool for the CAL dataflow language. It is integrated with the TINA model checker that we use to identify parallelisable cyclo-static actors in dynamic dataflow programs.

The broader aim of this work is to integrate automated formal verification into parallelising compilers and parallel runtime systems for heterogeneous architectures.

Speaker bio: Dr Rob Stewart is an Assistant Professor at Heriot-Watt University. He’s interested in formalising, verifying and implementing dataflow, functional and domain specific programming languages for manycore architectures and programmable hardware.

Abstract: It is well known that older adults continue to lag behind younger adults in terms of their breadth of uptake of digital technologies, amount and quality of engagement in these tools and ability to critically engage with the online world. Can these differences be explained by older adults’ distrust of digital technologies? Is trust, therefore, a critical design consideration for appealing to older adults? In this talk I will argue that while distrust is not, in fact, determinative of non-use and therefore does not explain these differences in tech usage, it is nonetheless key for designers to understand older adult distrust in developing socially responsible technologies.

Speaker Bio: Bran is a lecturer in the Data Science Institute at Lancaster University. Her research explores the social impacts of computing, with a particular interest in trust, privacy, and ethics. Her recent work has explored these issues at both ends of the age spectrum, with projects such as IoT4Kids, looking at the privacy, security and ethical issues of enabling children to programme IoT devices; and Mobile Age, looking at developing mobile apps for older adults. Bran currently serves as a member of the ACM Europe Technology Policy Committee.

Abstract:

Two important aspects in hardware design are the safe routing of signals between modules, and ensuring that ports are correctly connected. Well-known hardware description languages such as SystemVerilog, provide nominal checking over these aspects. Thus, leaving correctness checks over module orchestration to be performed post-design-time using static analyses, testing, and during synthesis.

Using a mixture of dependent and quantitative typing, we can lift external correctness checks over module connections directly into the type-system. With this approach we can detect more errors at design time, enhance the safety of our hardware designs, and thus increase design productivity.

In this talk I will introduce and discuss LightClick, an orchestration language for hardware design that exemplifies our approach. LightClick uses quantitative typing to ensure linear usage of ports, and dependent types to ensure that port compatibility is a decidable compile-time check. I will show how LightClick can be used to model simple hardware designs, how SystemVerilog stubs are generated from designs using staged interpretation.

Speaker Bio: Jan is a Research Associate at the University of Glasgow, who is interested in using state-of-the-art advances in programming language theory to build more trustworthy systems. Jan is currently involved in the Border Patrol project – a collaboration between the Universities of Heriot-Watt, Glasgow, and Imperial College London to explore how Dependent Typing and Session Typing can help make hardware design safer and secure.

Abstract:

This talk provides an insight into the challenges involved in providing near real-time news search to Bloomberg customers. It starts with a picture of what’s involved in building such a backend, then delves into what makes up a search engine. Finally we discuss the challenges of scaling up for low-latency and high-load, and how we tackle them.

Speaker Bio:

Ankush leads the News Search infrastructure team at the Bloomberg Engineering office in London. After completing his Masters in Computer Science, he joined Bloomberg at their New York office in 2009. Later working from Washington DC, he led a team to build a web application leveraging Lucene/Elasticsearch for businesses to discover government contracting opportunities. In London, his team focuses on search infrastructure and services allowing clients to search news events from all over the globe with near real-time access and sub-second latencies.