Systems Research

Fully funded PhD Scholarship in Hardware Simulation at Scale

 

As the Internet ofThings (IoT) expands, the number of connected devices is expected to reach close to 30 billion by 2030. These devices range from simple sensors to complex embedded systems, each with unique characteristics and communication protocols. Simulating such a vast and diverse array of devices presents a significant challenge in terms of scalability, accuracy, and efficiency. This PhD project aims to develop a comprehensive framework for simulating many (1000s, 10,000s, 1,000,000s) heterogeneous IoT devices, at (hopefully) close to real-time speeds. The project will focus on designing a specialised languages for describing hardware and simulations, creating an efficient simulation environment, and exploring hardware acceleration techniques to achieve high performance and scalability.

Previous research in this area has primarily focused on simulating individual devices, smaller networks, or using simplified models that do not fully capture the intricacies of real-world IoT systems. This project seeks to address these limitations by developing a scalable simulation framework that can accurately model the behaviour of billions of heterogeneous devices, advancing the state-of-the-art in simulation languages, distributed computing, and hardware acceleration.

The project will be structured around three core research ideas:

  • Simulation Languages for Heterogeneous Embedded Devices: The first research objective is to explore the creation of a specialised language for describing the behaviour and interactions of heterogeneous IoT devices. This language will need to be expressive enough to capture the wide range of device architectures and communication protocols found in IoT systems. The language will also support modularity and extensibility, allowing users to easily incorporate new device types and behaviours into the simulation.
  • Development of a Scalable Simulation Environment: The second research objective is to create a simulation environment that can efficiently emulate IoT devices at scale, across multiple simulation servers. This environment will be designed to support distributed computing, allowing for parallel execution of simulated devices across a large number of servers. The project will explore various techniques for load balancing, synchronisation, and communication between servers to ensure that the simulation remains efficient and accurate as the scale increases.
  • Hardware Acceleration for Large-Scale Simulations: The third research objective is to investigate the use of hardware acceleration techniques, such as Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs), to improve the performance of large-scale IoT simulations. This aspect of the project will focus on identifying the components of the simulation that can be offloaded to specialised hardware, and developing algorithms and architectures that leverage this hardware to achieve significant performance gains.

Topics of Interest

  • Heterogeneous Systems Modelling: Techniques for accurately modelling the diverse architectures and communication protocols of IoT devices.
  • Distributed Simulation: Methods for efficiently distributing simulations across multiple servers, including load balancing, synchronisation, and inter-server communication.
  • Simulation Languages: Design and implementation of specialised languages for describing complex IoT devices and networks.
  • Hardware Acceleration: Exploration of FPGA, GPU, and other hardware acceleration technologies to enhance the performance of large-scale simulations.
  • Scalability and Performance Optimisation: Strategies for ensuring that the simulation framework can handle the increasing complexity and scale of IoT networks.
  • Validation and Verification: Techniques for validating and verifying the accuracy and reliability of large-scale IoT simulations.

The Scholarship

We have one fully-funded scholarship available, starting in September 2025, which will be awarded to competitively to the best applicant. The scholarship covers all tuition fees (irrespective of country of origin) and comes with a stipend valued at £19,705 per annum. More details can be found here: https://blogs.cs.st-andrews.ac.uk/csblog/2024/10/24/phd-studentships-available-for-2025-entry/

International applications are welcome. We especially encourage female applicants and underrepresented minorities to apply. The School of Computer Science was awarded the Athena SWAN Silver award for its sustained progression in advancing equality and representation, and we welcome applications from those suitably qualified from all genders, all races, ethnicities and nationalities, LGBT+, all or no religion, all social class backgrounds, and all family structures to apply for our postgraduate research programmes.

To Apply

Informal enquiries can be directed to Tom Spink. Full instructions for formal applications can be found at https://www.st-andrews.ac.uk/computer-science/prospective/pgr/how-to-apply/

The deadline for applications is 1 March 2025.

Fully-funded PhD scholarship in parallel programming and dependent-types

The school of Computer Science at the University of St Andrews has a fully-funded scholarship available working in the Programming Languages Research Group with Dr Christopher Brown. Applications must be received by 1 March 2025.

Background

Algorithmic skeletons provide a convenient and high-level approach to writing efficient parallel software by leveraging common patterns of parallel behaviours. A skeleton library presents the programmer with a library of high-level parallel interfaces, abstracting away the low-level complexities of manually handling concurrency primitives, e.g. locking, synchronisation and thread creation. Skeletons give an excellent compromise between ease of programming and the ability to generate highly efficient parallel software. A wide range of skeletons have been developed for several different languages, including Fastflow, TBB, PPL and OpenMP. However, despite the proliferation of skeleton libraries, there is little support for an increasingly popular class of programming languages equipped with dependent types.

 

Dependently-typed programming languages address the problem of program safety by ensuring that code conforms to its specification. This is achieved by permitting types to depend on values, thereby allowing programmers to express logical properties, and proof, as intrinsic parts of their programs. This conformance is checked at compile-time. This interest in dependent-types has resulted in a number of functional languages such as pi-forall, Agda, Idris and Coq. However, despite these developments in types, these dependently-typed languages still lack a parallel implementation, making development of safe parallel programs impossible.

 

This project will explore approaches to designing and implementing a dependently-typed parallel programming language. These approaches will consider the technical challenges, but also balancing those with the high-level usability that skeletons bring and the performance expectations of a performant system. As part of this exploration, use-cases will also need to be developed, and the scientific evaluation of the performance of the system will need to be carried out.

Topics of Interest

This project is largely exploratory in nature, and may take several different approaches and directions, including (but not limited to):

  • Extending an existing dependently-typed language, such as Idris, with new concurrency primitives.
  • Designing and implementing an efficient parallel runtime system as a backend to the language.
  • Building on top of these primitives to provide dependently-typed concurrency behaviours, such as synchronisation points, channel behaviours, etc.
  • To design and implement a set of dependently-typed algorithmic skeletons such as farms and pipelines.
  • To explore and identify new skeletons that arise from writing dependently-typed programs.
  • To use dependent-types to encode safety and soundness properties and reason about these properties in a formal way.

The Scholarship

We have one fully-funded scholarship available, starting in September 2025, which will be awarded to competitively to the best applicant. The scholarship covers all tuition fees (irrespective of country of origin) and comes with a stipend valued at £19,705 per annum. More details can be found here: https://blogs.cs.st-andrews.ac.uk/csblog/2024/10/24/phd-studentships-available-for-2025-entry/

International applications are welcome. We especially encourage female applicants and underrepresented minorities to apply. The School of Computer Science was awarded the Athena SWAN Silver award for its sustained progression in advancing equality and representation, and we welcome applications from those suitably qualified from all genders, all races, ethnicities and nationalities, LGBT+, all or no religion, all social class backgrounds, and all family structures to apply for our postgraduate research programmes.

To Apply

Informal enquiries can be directed to Chris. Full instructions for formal applications can be found at https://www.st-andrews.ac.uk/computer-science/prospective/pgr/how-to-apply/

The deadline for applications is 1 March 2025.

 

Fully-funded PhD scholarship in Privacy and Trust on the Web

As part of their efforts to enhance privacy and trust on the Web, many applications need to be able to determine whether or not a relationship exists between different entities. For example, it is desirable for web browsers to be able to determine that two domain names are under the same administrative control, such that cookies and other data can be safely shared between them. While determining these relationships might be easy for humans, it is impossible to do so algorithmically.

This project will explore approaches to the defining and enforcing organisational boundaries on the Internet. These approaches will consider the technical challenges, balancing those with user behaviour and expectations, and regulatory considerations. This will include identifying use cases, evaluating and measuring existing and proposed approaches, and developing and implementing novel techniques. Where appropriate, this will involve engagement with standards development organisations, including the World Wide Web Consortium (W3C) and the Internet Engineering Task Force (IETF). Continue reading

PhD success for a former graduate

Last month Professor Simon Dobson was invited to be on the PhD examining committee for Indushree Banerjee at TU Delft.

PhD examining committee, paranymphs, and family

She passed with flying colours, for her thesis on ad hoc network protocols for use in disaster recovery situations. The protocol is designed around a very strong model of social justice and equality, working on low-power mobile devices and operating so as to conserve power reserves and device lifetime over the important 48-hour initial period of disaster relief.

Indushree did her MSc in St Andrews ten years ago, which gives us the opportunity for a couple of before-and-after photographs.

Simon and Indushree, MSc graduation 2012 Simon and Indushree, PhD graduation 2022

Neither of them seem to have changed all that much, apart from Simon having gone “Full Gandalf” during lockdown.

Indushree is now doing a postdoc in Delft, focusing on technology applied to  wildlife conservation and ecology. We’re hoping to get her over for a seminar in the new year.

Systems Research Group seminars

The Systems Research Group is re-starting their seminars series from 6th May 2022. Seminars will take place every two weeks at 1pm, on Fridays. From May to July the seminars will be online (SRG Teams), while from September onward we aim to move them to a hybrid format. More information on the schedule can be found on the seminars page of the Systems Research Group site.

Donald Robertson awarded Brendan Murphy Prize at MSN/Cosener’s 2019!

Each year in July, the (broadly-defined) computer networking community converges at Cosener’s House for the MSN workshop. The workshop is an informal gathering where attendees – students in particular – are encouraged to present on-going work and/or crazy ideas. From among the  presentations, the Brendan Murphy Award is given to the best student presentation, generally for work that has yet to be scrutinized or peer-reviewed.

Congratulations to Donald Robertson who, this year, has brought that honour to St Andrews as co-recipient of the award (alongside Naomi Arnold from QMUL).

http://coseners.net/history/brendan-murphy-prize/

(In the interest of transparency, Marwan Fayed was on the judging panel but recused himself during discussion of Donald’s presentation.)

SRG Seminar: “Large-Scale Hierarchical k-means for Heterogeneous Many-Core Supercomputers” by Teng Yu

We present a novel design and implementation of k-means clustering algorithm targeting supercomputers with heterogeneous many-core processors. This work introduces a multi-level parallel partition approach that not only partitions by dataflow and centroid, but also by dimension. Our multi-level ($nkd$) approach unlocks the potential of the hierarchical parallelism in the SW26010 heterogeneous many-core processor and the system architecture of the supercomputer.
Our design is able to process large-scale clustering problems with up to 196,608 dimensions and over 160,000 targeting centroids, while maintaining high performance and high scalability, significantly improving the capability of k-means over previous approaches. The evaluation shows our implementation achieves performance of less than 18 seconds per iteration for a large-scale clustering case with 196,608 data dimensions and 2,000 centroids by applying 4,096 nodes (1,064,496 cores) in parallel, making k-means a more feasible solution for complex scenarios.
This work is to be presented in the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC18).

Event details

  • When: 1st November 2018 13:00 - 14:00
  • Where: Cole 1.33b
  • Series: Systems Seminars Series
  • Format: Seminar, Talk

SRG Seminar: “Using Metric Space Indexing for Complete and Efficient Record Linkage” by Özgür Akgün

Record linkage is the process of identifying records that refer to the same real-world entities, in situations where entity identifiers are unavailable. Records are linked on the basis of similarity between common attributes, with every pair being classified as a link or non-link depending on their degree of similarity. Record linkage is usually performed in a three-step process: first groups of similar candidate records are identified using indexing, pairs within the same group are then compared in more detail, and finally classified. Even state-of-the-art indexing techniques, such as Locality Sensitive Hashing, have potential drawbacks. They may fail to group together some true matching records with high similarity. Conversely, they may group records with low similarity, leading to high computational overhead. We propose using metric space indexing to perform complete record linkage, which results in a parameter-free record linkage process combining indexing, comparison and classification into a single step delivering complete and efficient record linkage. Our experimental evaluation on real-world datasets from several domains shows that linkage using metric space indexing can yield better quality than current indexing techniques, with similar execution cost, without the need for domain knowledge or trial and error to configure the process.

Event details

  • When: 18th October 2018 13:00 - 14:00
  • Where: Cole 1.33b
  • Series: Systems Seminars Series
  • Format: Seminar

SRG Seminar: “Efficient Cross-architecture Hardware Virtualisation” by Tom Spink

Virtualisation is a powerful tool used for the isolation, partitioning, and sharing of physical computing resources. Employed heavily in data centres, becoming increasingly popular in industrial settings, and used by home-users for running alternative operating systems, hardware virtualisation has seen a lot of attention from hardware and software developers over the last ten?fifteen years.

From the hardware side, this takes the form of so-called hardware assisted virtualisation, and appears in technologies such as Intel-VT, AMD-V and ARM Virtualization Extensions. However, most forms of hardware virtualisation are typically same-architecture virtualisation, where virtual versions of the host physical machine are created, providing very fast isolated instances of the physical machine, in which entire operating systems can be booted. But, there is a distinct lack of hardware support for cross-architecture virtualisation, where the guest machine architecture is different to the host.

I will talk about my research in this area, and describe the cross-architecture virtualisation hypervisor Captive that can boot unmodified guest operating systems, compiled for one architecture in the virtual machine of another.

I will talk about the challenges of full system simulation (such as memory, instruction, and device emulation), our approaches to this, and how we can efficiently map guest behaviour to host behaviour.

Finally, I will discuss our plans for open-sourcing the hypervisor, the work we are currently doing and what future work we have planned.

Event details

  • When: 11th October 2018 13:00 - 14:00
  • Where: Cole 1.33b
  • Series: Systems Seminars Series
  • Format: Seminar, Talk

Dasip 2018 Keynote: Professor Simon Dobson

Head of School Simon Dobson will deliver a keynote at Dasip, the Conference on Design and Architectures for Signal and Image Processing in October in Porto. Dasip provides an international forum for innovation and developments in the field of embedded signal processing systems. Simon’s keynote will focus on making the transition from sensors to sensor systems software.

Abstract: Signal processing underpins everything we do with sensors. The physical limits of sensors, and the effects of their exposure to their environment, in turn constrain their accuracy, and therefore affect the trust we can place in sensor-driven systems. But this is a long pipeline, and it’s by no means clear how to trace from low-level errors and inaccuracies to their high-level consequences. In this talk I will try to tease-out some of the desiderata we might look for in such a pipeline, with a view to understanding how we can go about building sensor systems that deserve our trust.